1. Field of the Invention
The present invention relates to a semiconductor device having a logic unit, a storage unit, and a built-in self test (BIST) circuit, and particularly to improvement for preventing test by the BIST circuit from being interfered with by initial undefined value stored in the storage unit with simple structure.
2. Description of the Background Art
FIG. 10 is a block diagram showing the structure of a conventional semiconductor device as a background of the present invention. This semiconductor device 151 is constructed as a dedicated LSI for specific applications called ASIC (Application-Specific IC), which includes a RAM 10 as a storage unit and combinational logic circuits 40, 41, and 42 as logic units at the same time. It further includes a BIST circuit for executing BIST so as to easily and efficiently perform test to the ASIC formed as a VLSI with highly integrated circuit elements. The BIST is a method for facilitating test to semiconductor devices in which semiconductor devices are tested by themselves.
The BIST circuit has an LFSR (Linear Feedback Shift Register) 50 and an MISR (Multiple Input Signature Register) 51, and it also uses the scan test method. That is to say, storage elements such as flip-flops provided in peripheral parts of the RAM 10 and the combinational logic circuits 40, 41, 42 to achieve original functions of the device 151 (functions other than testing) are coupled in cascade in a freely coupled/decoupled manner to form scan paths 11 to 14, and 21 to 24.
The scan path 23 is located in the peripheral part of the combinational logic circuit 40. It is formed by coupling storage elements that exchange signals with the combinational logic circuit 40. Similarly, the scan path 24 is located in the peripheral part of the combinational logic circuits 41 and 42, which is formed by coupling storage elements that exchange signals with them.
The scan path 21 is formed by coupling storage elements interposed between the combinational logic circuit 40 and the combinational logic circuit 41 for exchanging signals, and the scan path 22 is formed by coupling storage elements interposed between the combinational logic circuit 40 and the combinational logic circuit 42 for exchanging signals. The scan paths 11 to 14 are each formed by coupling storage elements interposed between the RAM 10 and the combinational logic circuit 40 for exchanging signals between them.
These storage elements are coupled to each other only when test is performed, and they are decoupled in other operations. The BIST circuit performs test to the RAM 10 and the combinational logic circuits 40, 41, 42 in the device 151 through these scan paths 11 to 14, 21 to 24. The scan paths 21, 11 to 14, 22 are coupled to form one row of scan path. Three rows of scan paths, the scan path 23, the scan path 21, 11 to 14, 22, and the scan path 24, are interposed between the LFSR 50 and the MISR 51.
Usually, the storage elements like the FFs (flip-flops) forming the scan paths are elements provided in peripheral parts in logic units and storage units, to function as relay for exchange of signals with other units. That is, the storage elements forming the scan paths usually belong to some one of the units. For example, the part surrounded by the dotted line marked "1" in FIG. 10 corresponds to the original storage unit. However, for the purpose of clearly showing the relation between the scan paths and other parts, this specification defines the parts other than the scan paths as the combinational logic circuits (logic units) 40, 41, 42, and RAM (storage unit) 10, as shown in the drawings including FIG. 10.
FIG. 11 is a block diagram showing the inside structure of the LFSR 50. The LFSR 50 includes a plurality of FFs 61 coupled in cascade to each other and an EXOR (exclusive OR element) 62 for connecting them in a circulating manner. The FFs 61 hold and output input signals in synchronization with a clock signal (not shown). Accordingly after the FFs 61 have been supplied with given initial value for initialization, pseudo-random numbers with circulating period determined by the number of FFs 61 coupled in cascade sequentially appear at the outputs of the FFs 61 in synchronization with the clock signal and transferred to the following FFs 61.
In the example shown in FIG. 11, 22 FFs 61 are coupled in cascade and therefore 2.sup.22 -1 pseudo-random numbers are periodically generated. Three of the 22 outputs are respectively supplied to the three rows of scan paths. That is, the LFSR 50 is configured as a kind of test pattern generator (TPG) circuit for generating test patterns for BIST and supplying them to a row or a plurality of rows of scan paths.
FIG. 12 is a block diagram showing the internal structure of the MISR 51. The MISR 51 has a plurality of circuits coupled in cascade each including an FF 63 and an EXOR 64, and an EXOR 65 for coupling those circuits in a circulating manner. Signals inputted to the EXORs 64 in synchronization with a clock signal not shown are subjected to certain operation, and then the operated signals are outputted from the final-stage FF 63 as signature SO. The signature SO corresponds to a signal obtained by compacting the signals inputted to one or a plurality of EXORs 64 along time series and (in the case of multiple inputs) along the space.
In the example shown in FIG. 12, 22 circuits are coupled in cascade, and signals from the three rows of scan paths are supplied to three of the 22 inputs. Then the information about the results obtained by testing the individual parts in the device 151 supplied through the scan paths is integrated into the signature SO. Thus, the MISR 51 is configured as a kind of output data compactor (ODC) circuit for compacting signals containing information about test results supplied from a row or a plurality of rows of scan paths, i.e., signals representing test results.
The signature SO is transferred out of the device 151 through a pin (not shown) to be used as expected value for the test results. A comparison in pattern is made between the normal value for the signature SO obtained by performing logical simulation to the device 151 and the real value of the signature SO held in the MISR 51 to determine whether the combinational logic circuits 40, 41, 42 and the RAM 10, including the scan paths, are normal. In this way, the presence of the BIST circuit enables individual parts in the device 151 to be tested just by comparing the value of signature SO outputted from the device 151 itself with the normal value.
FIG. 13 is a block diagram fully showing the scan paths 13 and 14 interposed between the combinational logic circuit 40 and the RAM 10. The scan path 13 is formed by coupling three FFs 71 in cascade which are interposed between the combinational logic circuit 40 and the RAM 10, for receiving signal outputs from the combinational logic circuit 40 and sending them as data signals to data input portions di[n] (n=0, 1, 2) of the RAM 10.
The FFs 71 are coupled with the respective preceding FFs 71 through selectors 72. An SFF (scan flip-flop, generally "a scan storage element") 2 is usually configured by adding a selector 72 required for test to an FF 71 used to allow the device 151 to achieve its original (i.e., designed) function. A plurality of SFFs 2 are coupled in cascade to form the scan path 13. This structure is the same with other scan paths. The FFs 71 in the SFFs 2 forming the scan path 14 receive data signals (storage data signals) outputted from the data output portions do[n] of the RAM 10 and send them to the combinational logic circuit 40.
Each selector 72 is responsive to the value of a scan mode signal SM inputted as a select signal to select one of its two input signals. Specifically, when the scan mode signal SM is 0, the selectors 72 in the scan path 13 select output signals from the combinational logic circuit 40, and those in the scan path 14 select data signals outputted from the data output portions do[n] of the RAM 10. As a result, the SFFs 2 (and the FFs 71) are decoupled from each other and the FFs 71 perform their original function of receiving/sending signals between the units in synchronization with a clock signal.
When the scan mode signal SM is 1, the selectors 72 in the scan paths 13 and 14 select output signals from the preceding SFFs 2. As a result, the SFFs 2 (and the FFs 71) are coupled in cascade to each other, including the coupling of the scan paths 13 and 14, to send output signals from the preceding SFFs 2 to the following SFFs 2 in synchronization with the clock signal.
In this specification, the number of the SFFs 2 forming a scan path is referred to as the number of stages of the scan path. In the example shown in FIG. 13, the scan paths 13 and 14 are each formed of three SFFs 2. Accordingly, the scan paths 13 and 14 are both referred to as "a scan path with three stages." Referring to FIG. 10 again, the BIST circuit in the device 151 has a control circuit not shown, in addition to the LFSR 50 and MISR 51. The scan mode signal SM is supplied to all scan paths in the device 151 by the control circuit. Except when the device 151 performs a test, "0" is supplied as the scan mode signal SM to allow the device 151 to achieve its original function other than test.
When performing a test, "1" is supplied as the scan mode signal SM, so that pseudo-random numbers outputted from the LFSR 50 are sequentially supplied to the multiple-stage SFFs 2 belonging to the three scan paths. At the same time, the pseudo-random numbers held in the SFFs 2 are also inputted to the units connected to the outputs of the SFFs 2. When the pseudo-random numbers supplied from the LFSR 50 have been delivered to all SFFs 2 in the longest (with the largest number of SFFs 2) scan path among the three rows of scan paths, the scan mode signal SM changes from 1 to 0 only in one clock period. This causes the SFFs 2 belonging to the respective scan paths to capture signals outputted from the individual units.
In the example of the scan paths 13 and 14 shown in FIG. 13, when the scan mode signal SM is 0, the SFFs 2 belonging to the scan path 13 capture output signals from the combinational logic circuit 40 and the SFFs 2 belonging to the scan path 14 capture data signals from the data output portions do[n]. Then the value of the scan mode signal SM returns to 1. As a result, the output signals captured from the respective units are transferred along the scan paths into the MISR 51. Then the MISR 51 outputs, for each clock, the signature SO obtained by applying operation to the output signals from the units coming through the scan paths.
[0021] When all the output signals from the respective units captured into the scan paths have been collected into the MISR 51, new pseudo-random numbers are supplied from the LFSR 50 are held in all of SFFs 2 belonging to the respective scan paths. At this instant, the scan mode signal SM changes from 1 to 0 only for one clock period again.
As described above, for each given period in which pseudo-random numbers from the LFSR 50 are delivered to all SFFs 2 in all scan paths, the scan mode signal SM changes from 1 to 0 only for one clock period. Then the pseudo-random numbers as test pattern are supplied as input signals to the individual units and the output signals provided from the individual units in response to their input signals are collected into the MISR 51 and compacted to the signature SO.
The scan path 14 captures data signals outputted from the data output portions do[n] of the RAM 10. This causes the following problem. When a test is started without initializing memory cells (not shown) in the RAM 10, data signals with undefined value stored in the memory cells will be captured into the scan path 14.
As a result, the undefined value is mixed into the MISR 51, then all obtained as the signature SO will be unpredictable undefined value. If the MISR 51 receives undefined value even only at one of its plurality of inputs or even in one clock period, the influence appears in the signature SO, and in all over the entirety of the following signature SO. Accordingly, it is necessary when testing the device 151 to avoid inclusion of undefined value in any SFF 2 in any scan path and also in any clock period.
No undefined value is mixed into the scan paths from the combinational logic circuits 40, 41, 42, unless they are in a state to be determined as malfunction. However, undefined value may be mixed from the RAM 10 when it is not initialized, even if the RAM 10 is normal (i.e., good). In an ordinary scan test not using the BIST, it is possible to perform a normal test by discarding (masking) data including undefined value. However, in the BIST circuit, as stated above, once undefined value is mixed, the signature SO cannot be correctly obtained any more.
FIG. 14 is a block diagram showing part of a semiconductor device constructed to solve this problem. This device 152 has a RAM-BIST circuit 80. The RAM-BIST circuit 80 is a circuit for applying BIST to the RAM 10, which is disclosed in Japanese Patent Laying-Open No.8-94718, for example. Selectors 81, 82, 83 and 84 are interposed between the scan path 21 and the scan path 11, the scan paths 11 and 12, the scan paths 12 and 13, and the scan paths 13 and 14, respectively.
The selectors 81 to 84 each receive two output signals, an output signal from the preceding scan path and one of the output signals SIW, SIA, SIDI, SIDO from the RAM-BIST circuit 80. The selectors 81 to 84 are responsive to a select signal MEM outputted from the RAM-BIST circuit 80 to select one of their respective two input signals and output it. Each SFF 2 has the internal structure shown in FIG. 15.
An OR element (logic al OR element) 85 is connected to the write enable signal input portion "wec" for inputting a signal instructing write enable to the RAM 10. A signal corresponding to OR of the output signal from the scan path 11 and a write inhibit signal WINH included in the output signals from the RAM-BIST circuit 80 is inputted thereto.
First, the RAM 10 is initialized by the following procedure. The select signal MEM is set as MEM=1 and then the output signals SIW, SIA, SIDI, SIDO from the RAM-BIST circuit 80 are selected by the selectors 81 to 84. The output signal SIW is set as SIW=0 and the write inhibit signal WINH as WINH=0. Then 0 is inputted to the write enable signal input portion wec to enable writing of data signal into the RAM 10.
As the output signal SIA, all address signals are outputted to address all memory cells included in the RAM 10. As a result, all address signals are inputted to the address signal input portions a[n] of the RAM 10. In this period, the output signal SIDI is outputted as SIDI=0, for example. Accordingly, 0 is written into all memory cells as initial value. The RAM 10 is initialized in this way.
After the initialization, the select signal MEM is set as MEM=0. As a result, the selectors 81 to 84 select output signals from the preceding scan paths. That is to say, when the scan mode signal SM=1, the scan paths 21, 11 to 14, and 22 are coupled in this order to form a row of scan path. Further, the write inhibit signal WINH is set as WINH=1. As a result, write into the RAM 10 is inhibited. In this state, the RAM 10 and the combinational logic circuits 40, 41, 42 are tested by the LFSR 50 and the MISR 51. Since all memory cells in the RAM 10 have been initialized, no undefined value will be mixed into the MISR 51.
However, with the conventional device 152, the RAM 10 is initialized and then all units in the device 152 including the RAM 10 are tested, which introduces the problem that BIST to the logic units requires a long test time.
To solve this problem, Japanese Patent Laying-Open No.9-5403 discloses a device in which part of the scan path is branched. In this device, a scan path which may capture undefined value is branched to prevent inclusion of undefined value into the MISR. However, with this device, commercially available CAD tools for design-fortestability cannot be used for logical simulation, rule check, etc., because of the presence of the branched scan path.